STMicroelectronics /STM32G051 /RNG /RNG_SR

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Interpret as RNG_SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DRDY 0 (B_0x0)CECS 0 (B_0x0)SECS 0 (B_0x0)CEIS 0 (B_0x0)SEIS

CECS=B_0x0, CEIS=B_0x0, SEIS=B_0x0, SECS=B_0x0, DRDY=B_0x0

Description

status register

Fields

DRDY

Data Ready Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. Note: The DRDY bit can rise when the peripheral is disabled (RNGEN=0 in the RNG_CR register). If IE=1 in the RNG_CR register, an interrupt is generated when DRDY=1.

0 (B_0x0): The RNG_DR register is not yet valid, no random data is available.

1 (B_0x1): The RNG_DR register contains valid random data.

CECS

Clock error current status Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0.

0 (B_0x0): The RNG clock is correct (fRNGCLK> fHCLK/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.

1 (B_0x1): The RNG clock is too slow (fRNGCLK< fHCLK/32).

SECS

Seed error current status One of the noise source has provided more than 64 consecutive bits at a constant value (“0” or “1”), or more than 32 consecutive occurrence of two bit patterns (“01” or “10”) Both noise sources have delivered more than 32 consecutive bits at a constant value (“0” or “1”), or more than 16 consecutive occurrence of two bit patterns (“01” or “10”)

0 (B_0x0): No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.

1 (B_0x1): At least one of the following faulty sequence has been detected:

CEIS

Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.

0 (B_0x0): The RNG clock is correct (fRNGCLK> fHCLK/32)

1 (B_0x1): The RNG has been detected too slow (fRNGCLK< fHCLK/32)

SEIS

Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.

0 (B_0x0): No faulty sequence detected

1 (B_0x1): At least one faulty sequence has been detected. See SECS bit description for details.

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