STMicroelectronics /STM32G070 /RCC /AHBSMENR

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Interpret as AHBSMENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA1SMEN)DMA1SMEN 0 (DMA2SMEN)DMA2SMEN 0 (FLASHSMEN)FLASHSMEN 0 (SRAMSMEN)SRAMSMEN 0 (CRCSMEN)CRCSMEN

Description

AHB peripheral clock enable in Sleep mode register

Fields

DMA1SMEN

DMA1 clock enable during Sleep mode

DMA2SMEN

DMA2 clock enable during Sleep mode

FLASHSMEN

Flash memory interface clock enable during Sleep mode

SRAMSMEN

SRAM clock enable during Sleep mode

CRCSMEN

CRC clock enable during Sleep mode

Links

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