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STMicroelectronics /STM32G070 /RCC /APBRSTR1

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Interpret as APBRSTR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM3RST)TIM3RST 0 (TIM4RST)TIM4RST 0 (TIM6RST)TIM6RST 0 (TIM7RST)TIM7RST 0 (USART5RST)USART5RST 0 (USART6RST)USART6RST 0 (USBRST)USBRST 0 (SPI2RST)SPI2RST 0 (SPI3RST)SPI3RST 0 (USART2RST)USART2RST 0 (USART3RST)USART3RST 0 (USART4RST)USART4RST 0 (I2C1RST)I2C1RST 0 (I2C2RST)I2C2RST 0 (I2C3RST)I2C3RST 0 (DBGRST)DBGRST 0 (PWRRST)PWRRST

Description

APB peripheral reset register 1

Fields

TIM3RST

TIM3 timer reset
TIM4RST

TIM4 timer reset
TIM6RST

TIM6 timer reset
TIM7RST

TIM7 timer reset
USART5RST

USART5RST
USART6RST

USART6RST
USBRST

USBRST
SPI2RST

SPI2 reset
SPI3RST

SPI3 reset
USART2RST

USART2 reset
USART3RST

USART3 reset
USART4RST

USART4 reset
I2C1RST

I2C1 reset
I2C2RST

I2C2 reset
I2C3RST

I2C3RST reset
DBGRST

Debug support reset
PWRRST

Power interface reset

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data