ALRBWF=B_0x0, RSF=B_0x0, WUTWF=B_0x0, ALRAWF=B_0x0, INITF=B_0x0, SHPF=B_0x0, INITS=B_0x0, INIT=B_0x0
RTC initialization control and status register
| ALRAWF | Alarm A write flag This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0 (B_0x0): Alarm A update not allowed 1 (B_0x1): Alarm A update allowed |
| ALRBWF | Alarm B write flag This bit is set by hardware when alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0 (B_0x0): Alarm B update not allowed 1 (B_0x1): Alarm B update allowed |
| WUTWF | Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0 (B_0x0): Wakeup timer configuration update not allowed except in initialization mode 1 (B_0x1): Wakeup timer configuration update allowed |
| SHPF | Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 0 (B_0x0): No shift operation is pending 1 (B_0x1): A shift operation is pending |
| INITS | Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 0 (B_0x0): Calendar has not been initialized 1 (B_0x1): Calendar has been initialized |
| RSF | Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0 (B_0x0): Calendar shadow registers not yet synchronized 1 (B_0x1): Calendar shadow registers synchronized |
| INITF | Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0 (B_0x0): Calendar registers update is not allowed 1 (B_0x1): Calendar registers update is allowed |
| INIT | Initialization mode 0 (B_0x0): Free running mode 1 (B_0x1): Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. |
| RECALPF | Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to . |