CCDS=B_0x0, OIS1=B_0x0, MMS=B_0x0, OIS2=B_0x0, OIS1N=B_0x0, CCUS=B_0x0, TI1S=B_0x0, CCPC=B_0x0
control register 2
| CCPC | Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output. 0 (B_0x0): CCxE, CCxNE and OCxM bits are not preloaded 1 (B_0x1): CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). |
| CCUS | Capture/compare control update selection Note: This bit acts only on channels that have a complementary output. 0 (B_0x0): When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1 (B_0x1): When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. |
| CCDS | Capture/compare DMA selection 0 (B_0x0): CCx DMA request sent when CCx event occurs 1 (B_0x1): CCx DMA requests sent when update event occurs |
| MMS | Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 0 (B_0x0): Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 1 (B_0x1): Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 2 (B_0x2): Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 3 (B_0x3): Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 4 (B_0x4): Compare - OC1REFC signal is used as trigger output (TRGO). 5 (B_0x5): Compare - OC2REFC signal is used as trigger output (TRGO). |
| TI1S | TI1 selection 0 (B_0x0): The TIMx_CH1 pin is connected to TI1 input 1 (B_0x1): The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) |
| OIS1 | Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 0 (B_0x0): OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1 (B_0x1): OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 |
| OIS1N | Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register). 0 (B_0x0): OC1N=0 after a dead-time when MOE=0 1 (B_0x1): OC1N=1 after a dead-time when MOE=0 |
| OIS2 | Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register). 0 (B_0x0): OC2=0 when MOE=0 1 (B_0x1): OC2=1 when MOE=0 |