MSM=B_0x0, SMS2=B_0x0, TS2=B_0x0, TS1=B_0x0, SMS1=B_0x0
slave mode control register
| SMS1 | Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 (B_0x0): Slave mode disabled - if CEN = '1â then the prescaler is clocked directly by the internal clock. 4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 8 (B_0x8): Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. |
| TS1 | Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 0 (B_0x0): Internal Trigger 0 (ITR0) 1 (B_0x1): Internal Trigger 1 (ITR1) 2 (B_0x2): Internal Trigger 2 (ITR2) 3 (B_0x3): Internal Trigger 3 (ITR3) 4 (B_0x4): TI1 Edge Detector (TI1F_ED) 5 (B_0x5): Filtered Timer Input 1 (TI1FP1) 6 (B_0x6): Filtered Timer Input 2 (TI2FP2) |
| MSM | Master/slave mode 0 (B_0x0): No action 1 (B_0x1): The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. |
| SMS2 | Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer. 0 (B_0x0): Slave mode disabled - if CEN = '1â then the prescaler is clocked directly by the internal clock. 4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 8 (B_0x8): Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. |
| TS2 | Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 0 (B_0x0): Internal Trigger 0 (ITR0) 1 (B_0x1): Internal Trigger 1 (ITR1) 2 (B_0x2): Internal Trigger 2 (ITR2) 3 (B_0x3): Internal Trigger 3 (ITR3) 4 (B_0x4): TI1 Edge Detector (TI1F_ED) 5 (B_0x5): Filtered Timer Input 1 (TI1FP1) 6 (B_0x6): Filtered Timer Input 2 (TI2FP2) |