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STMicroelectronics /STM32G0B1 /DAC /DAC_SHRR

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Interpret as DAC_SHRR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TREFRESH10TREFRESH2

Description

DAC Sample and Hold refresh time register

Fields

TREFRESH1

DAC channel1 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN1=0.
TREFRESH2

DAC channel2 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs. Refer to implementation.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data