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STMicroelectronics /STM32G0B1 /DAC /DAC_SHSR2

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Interpret as DAC_SHSR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TSAMPLE2

Description

DAC Sample and Hold sample time register 2

Fields

TSAMPLE2

DAC channel2 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is low, if BWST2=1, the write operation is ignored.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data