STMicroelectronics /STM32G0B1 /FDCAN1 /FDCAN_IR

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Interpret as FDCAN_IR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RF0N 0 (B_0x0)RF0F 0 (B_0x0)RF0L 0 (B_0x0)RF1N 0 (B_0x0)RF1F 0 (B_0x0)RF1L 0 (B_0x0)HPM 0 (B_0x0)TC 0 (B_0x0)TCF 0 (B_0x0)TFE 0 (B_0x0)TEFN 0 (B_0x0)TEFF 0 (B_0x0)TEFL 0 (B_0x0)TSW 0 (B_0x0)MRAF 0 (B_0x0)TOO 0 (B_0x0)ELO 0 (B_0x0)EP 0 (B_0x0)EW 0 (B_0x0)BO 0 (B_0x0)WDI 0 (B_0x0)PEA 0 (B_0x0)PED 0 (B_0x0)ARA

WDI=B_0x0, RF1F=B_0x0, PED=B_0x0, MRAF=B_0x0, BO=B_0x0, EP=B_0x0, TCF=B_0x0, TSW=B_0x0, TFE=B_0x0, TEFF=B_0x0, TOO=B_0x0, TEFL=B_0x0, RF1L=B_0x0, RF0N=B_0x0, EW=B_0x0, HPM=B_0x0, RF0L=B_0x0, TEFN=B_0x0, PEA=B_0x0, RF1N=B_0x0, ARA=B_0x0, RF0F=B_0x0, ELO=B_0x0, TC=B_0x0

Description

FDCAN interrupt register

Fields

RF0N

Rx FIFO 0 new message

0 (B_0x0): No new message written to Rx FIFO 0

1 (B_0x1): New message written to Rx FIFO 0

RF0F

Rx FIFO 0 full

0 (B_0x0): Rx FIFO 0 not full

1 (B_0x1): Rx FIFO 0 full

RF0L

Rx FIFO 0 message lost

0 (B_0x0): No Rx FIFO 0 message lost

1 (B_0x1): Rx FIFO 0 message lost

RF1N

Rx FIFO 1 new message

0 (B_0x0): No new message written to Rx FIFO 1

1 (B_0x1): New message written to Rx FIFO 1

RF1F

Rx FIFO 1 full

0 (B_0x0): Rx FIFO 1 not full

1 (B_0x1): Rx FIFO 1 full

RF1L

Rx FIFO 1 message lost

0 (B_0x0): No Rx FIFO 1 message lost

1 (B_0x1): Rx FIFO 1 message lost

HPM

High-priority message

0 (B_0x0): No high-priority message received

1 (B_0x1): High-priority message received

TC

Transmission completed

0 (B_0x0): No transmission completed

1 (B_0x1): Transmission completed

TCF

Transmission cancellation finished

0 (B_0x0): No transmission cancellation finished

1 (B_0x1): Transmission cancellation finished

TFE

Tx FIFO empty

0 (B_0x0): Tx FIFO non-empty

1 (B_0x1): Tx FIFO empty

TEFN

Tx event FIFO New Entry

0 (B_0x0): Tx event FIFO unchanged

1 (B_0x1): Tx handler wrote Tx event FIFO element.

TEFF

Tx event FIFO full

0 (B_0x0): Tx event FIFO Not full

1 (B_0x1): Tx event FIFO full

TEFL

Tx event FIFO element lost

0 (B_0x0): No Tx event FIFO element lost

1 (B_0x1): Tx event FIFO element lost

TSW

Timestamp wraparound

0 (B_0x0): No timestamp counter wrap-around

1 (B_0x1): Timestamp counter wrapped around

MRAF

Message RAM access failure The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted Operation Mode (see mode). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM.

0 (B_0x0): No Message RAM access failure occurred

1 (B_0x1): Message RAM access failure occurred

TOO

Timeout occurred

0 (B_0x0): No timeout

1 (B_0x1): Timeout reached

ELO

Error logging overflow

0 (B_0x0): CAN error logging counter did not overflow.

1 (B_0x1): Overflow of CAN error logging counter occurred.

EP

Error passive

0 (B_0x0): Error_Passive status unchanged

1 (B_0x1): Error_Passive status changed

EW

Warning status

0 (B_0x0): Error_Warning status unchanged

1 (B_0x1): Error_Warning status changed

BO

Bus_Off status

0 (B_0x0): Bus_Off status unchanged

1 (B_0x1): Bus_Off status changed

WDI

Watchdog interrupt

0 (B_0x0): No message RAM watchdog event occurred

1 (B_0x1): Message RAM watchdog event due to missing READY

PEA

Protocol error in arbitration phase (nominal bit time is used)

0 (B_0x0): No protocol error in arbitration phase

1 (B_0x1): Protocol error in arbitration phase detected (PSR.LEC different from 0,7)

PED

Protocol error in data phase (data bit time is used)

0 (B_0x0): No protocol error in data phase

1 (B_0x1): Protocol error in data phase detected (PSR.DLEC different from 0,7)

ARA

Access to reserved address

0 (B_0x0): No access to reserved address occurred

1 (B_0x1): Access to reserved address occurred

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