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STMicroelectronics /STM32G0B1 /FDCAN1 /FDCAN_RWD

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Interpret as FDCAN_RWD

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WDC0WDV

Description

FDCAN RAM watchdog register

Fields

WDC

Watchdog configuration Start value of the message RAM watchdog counter. With the reset value of 00, the counter is disabled. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of FDCAN_CCCR register are set to 1.
WDV

Watchdog value Actual message RAM watchdog counter value.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data