RF0L=B_0x0, F0F=B_0x0
FDCAN Rx FIFO 0 status register
| F0FL | Rx FIFO 0 fill level Number of elements stored in Rx FIFO 0, range 0 to 3. |
| F0GI | Rx FIFO 0 get index Rx FIFO 0 read index pointer, range 0 to 2. |
| F0PI | Rx FIFO 0 put index Rx FIFO 0 write index pointer, range 0 to 2. |
| F0F | Rx FIFO 0 full 0 (B_0x0): Rx FIFO 0 not full 1 (B_0x1): Rx FIFO 0 full |
| RF0L | Rx FIFO 0 message lost This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit is also reset. 0 (B_0x0): No Rx FIFO 0 message lost 1 (B_0x1): Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size 0 |