RF1L=B_0x0, F1F=B_0x0
FDCAN Rx FIFO 1 status register
| F1FL | Rx FIFO 1 fill level Number of elements stored in Rx FIFO 1, range 0 to 3. |
| F1GI | Rx FIFO 1 get index Rx FIFO 1 read index pointer, range 0 to 2. |
| F1PI | Rx FIFO 1 put index Rx FIFO 1 write index pointer, range 0 to 2. |
| F1F | Rx FIFO 1 full 0 (B_0x0): Rx FIFO 1 not full 1 (B_0x1): Rx FIFO 1 full |
| RF1L | Rx FIFO 1 message lost This bit is a copy of interrupt flag IR[RF1L]. When IR[RF1L] is reset, this bit is also reset. 0 (B_0x0): No Rx FIFO 1 message lost 1 (B_0x1): Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0 |