RX=B_0x0, TX=B_0x0, LBCK=B_0x0
FDCAN test register
| LBCK | Loop back mode 0 (B_0x0): Reset value, Loop Back mode is disabled 1 (B_0x1): Loop Back mode is enabled (see Power down (Sleep mode)) |
| TX | Control of transmit pin 0 (B_0x0): Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time 1 (B_0x1): Sample point can be monitored at pin FDCANx_TX 2 (B_0x2): Dominant (0) level at pin FDCANx_TX 3 (B_0x3): Recessive (1) at pin FDCANx_TX |
| RX | Receive pin Monitors the actual value of pin FDCANx_RX 0 (B_0x0): The CAN bus is dominant (FDCANx_RX = 0) 1 (B_0x1): The CAN bus is recessive (FDCANx_RX = 1) |