ETOC=B_0x0, TOS=B_0x0
FDCAN timeout counter configuration register
| ETOC | Timeout counter enable This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 (B_0x0): Timeout counter disabled 1 (B_0x1): Timeout counter enabled |
| TOS | Timeout select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1. 0 (B_0x0): Continuous operation 1 (B_0x1): Timeout controlled by Tx Event FIFO 2 (B_0x2): Timeout controlled by Rx FIFO 0 3 (B_0x3): Timeout controlled by Rx FIFO 1 |
| TOP | Timeout period Start value of the timeout counter (down-counter). Configures the timeout period. |