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STMicroelectronics /STM32G0B1 /FDCAN1 /FDCAN_TXBC

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Interpret as FDCAN_TXBC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TFQM

TFQM=B_0x0

Description

FDCAN Tx buffer configuration register

Fields

TFQM

Tx FIFO/queue mode This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

0 (B_0x0): Tx FIFO operation

1 (B_0x1): Tx queue operation.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data