EFF=B_0x0
FDCAN Tx event FIFO status register
| EFFL | Event FIFO fill level Number of elements stored in Tx event FIFO, range 0 to 3. |
| EFGI | Event FIFO get index Tx Event FIFO read index pointer, range 0 to 3. |
| EFPI | Event FIFO put index Tx Event FIFO write index pointer, range 0 to 3. |
| EFF | Event FIFO full 0 (B_0x0): Tx event FIFO not full 1 (B_0x1): Tx event FIFO full |
| TEFL | Tx Event FIFO element lost This bit is a copy of interrupt flag IR[TEFL]. When IR[TEFL] is reset, this bit is also reset. 0 No Tx event FIFO element lost 1 Tx event FIFO element lost, also set after write attempt to Tx Event FIFO of size 0. |