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STMicroelectronics /STM32G0B1 /LPUART1 /LPUART_RDR

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Interpret as LPUART_RDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDR

Description

LPUART receive data register

Fields

RDR

Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data