CKPOL=B_0x0, ASTRTEN=B_0x0, I2SCFG=B_0x0, I2SMOD=B_0x0, I2SSTD=B_0x0, PCMSYNC=B_0x0, I2SE=B_0x0, CHLEN=B_0x0, DATLEN=B_0x0
SPI_I2S configuration register
| CHLEN | Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. 0 (B_0x0): 16-bit wide 1 (B_0x1): 32-bit wide |
| DATLEN | Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode. 0 (B_0x0): 16-bit data length 1 (B_0x1): 24-bit data length 2 (B_0x2): 32-bit data length 3 (B_0x3): Not allowed |
| CKPOL | Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals. 0 (B_0x0): I2S clock inactive state is low level 1 (B_0x1): I2S clock inactive state is high level |
| I2SSTD | I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode. 0 (B_0x0): I2S Philips standard 1 (B_0x1): MSB justified standard (left justified) 2 (B_0x2): LSB justified standard (right justified) 3 (B_0x3): PCM standard |
| PCMSYNC | PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. 0 (B_0x0): Short frame synchronization 1 (B_0x1): Long frame synchronization |
| I2SCFG | I2S configuration mode Note: These bits should be configured when the I2S is disabled. They are not used in SPI mode. 0 (B_0x0): Slave - transmit 1 (B_0x1): Slave - receive 2 (B_0x2): Master - transmit 3 (B_0x3): Master - receive |
| I2SE | I2S enable Note: This bit is not used in SPI mode. 0 (B_0x0): I2S peripheral is disabled 1 (B_0x1): I2S peripheral is enabled |
| I2SMOD | I2S mode selection Note: This bit should be configured when the SPI is disabled. 0 (B_0x0): SPI mode is selected 1 (B_0x1): I2S mode is selected |
| ASTRTEN | Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information. 0 (B_0x0): The Asynchronous start is disabled. 1 (B_0x1): The Asynchronous start is enabled. |