KEYSIZE=B_0x0, DMAINEN=B_0x0, CCFIE=B_0x0, GCMPH=B_0x0, DMAOUTEN=B_0x0, CHMOD2=B_0x0, ERRC=B_0x0, MODE=B_0x0, NPBLB=B_0x0, ERRIE=B_0x0, DATATYPE=B_0x0, CHMOD1=B_0x0, CCFC=B_0x0, EN=B_0x0
AES control register
| EN | AES enable This bit enables/disables the AES peripheral: At any moment, clearing then setting the bit re-initializes the AES peripheral. This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| DATATYPE | Data type selection This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping: For more details, refer to . Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): None 1 (B_0x1): Half-word (16-bit) 2 (B_0x2): Byte (8-bit) 3 (B_0x3): Bit |
| MODE | AES operating mode This bitfield selects the AES operating mode: Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. Any attempt to selecting Mode 4 while either ECB or CBC chaining mode is not selected, defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4. 0 (B_0x0): Mode 1: encryption 1 (B_0x1): Mode 2: key derivation (or key preparation for ECB/CBC decryption) 2 (B_0x2): Mode 3: decryption 3 (B_0x3): Mode 4: key derivation then single decryption |
| CHMOD1 | Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): Electronic codebook (ECB) 1 (B_0x1): Cipher-Block Chaining (CBC) 2 (B_0x2): Counter Mode (CTR) 3 (B_0x3): Galois Counter Mode (GCM) and Galois Message Authentication Code (GMAC) 4 (B_0x4): Counter with CBC-MAC (CCM) |
| CCFC | Computation complete flag clear Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register: Reading the flag always returns zero. 0 (B_0x0): No effect 1 (B_0x1): Clear CCF |
| ERRC | Error flag clear Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register: Reading the flag always returns zero. 0 (B_0x0): No effect 1 (B_0x1): Clear RDERR and WRERR flags |
| CCFIE | CCF interrupt enable This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set: 0 (B_0x0): Disable (mask) 1 (B_0x1): Enable |
| ERRIE | Error interrupt enable This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is set: 0 (B_0x0): Disable (mask) 1 (B_0x1): Enable |
| DMAINEN | DMA input enable This bit enables/disables data transferring with DMA, in the input phase: When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| DMAOUTEN | DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation). Usage of DMA with Mode 4 (single decryption) is not recommended. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| GCMPH | GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield). 0 (B_0x0): Init phase 1 (B_0x1): Header phase 2 (B_0x2): Payload phase 3 (B_0x3): Final phase |
| CHMOD2 | Chaining mode selection, bit [2] Refer to the bits [5:6] of the register for the description of the CHMOD[2:0] bitfield CHMOD[1:0]: Chaining mode selection, bits [1:0] This bitfield, together with the bit CHMOD[2] forming CHMOD[2:0], selects the AES chaining mode: others: Reserved Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): Electronic codebook (ECB) 1 (B_0x1): Cipher-Block Chaining (CBC) 2 (B_0x2): Counter Mode (CTR) 3 (B_0x3): Galois Counter Mode (GCM) and Galois Message Authentication Code (GMAC) 4 (B_0x4): Counter with CBC-MAC (CCM) |
| KEYSIZE | Key size selection This bitfield defines the length of the key used in the AES cryptographic core, in bits: Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access. 0 (B_0x0): 128 1 (B_0x1): 256 |
| NPBLB | Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: … 0 (B_0x0): All bytes are valid (no padding) 1 (B_0x1): Padding for one least-significant byte of last block 15 (B_0xF): Padding for 15 least-significant bytes of last block |