Regviz

STMicroelectronics /STM32G473xx /DAC1 /DAC_SHRR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DAC_SHRR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32G473xx/DAC1/DAC_SHRR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TREFRESH10TREFRESH2

Description

DAC Sample and Hold refresh time register

Fields

TREFRESH1

DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI
TREFRESH2

DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data