RegViz: Visualize RCC_AHB1SMENR Bitfield

STMicroelectronics /STM32G473xx /RCC /RCC_AHB1SMENR

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Interpret as RCC_AHB1SMENR

SRAM1SMEN=B_0x0, FLASHSMEN=B_0x0, DMA2SMEN=B_0x0, DMA1SMEN=B_0x0, CRCSMEN=B_0x0, FMACSMEN=B_0x0, DMAMUX1SMEN=B_0x0, CORDICSMEN=B_0x0

Description

AHB1 peripheral clocks enable in Sleep and Stop modes register

Fields

DMA1SMEN	DMA1 clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): DMA1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): DMA1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
DMA2SMEN	DMA2 clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode. 0 (B_0x0): DMA2 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): DMA2 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
DMAMUX1SMEN	DMAMUX1 clock enable during Sleep and Stop modes. Set and cleared by software. 0 (B_0x0): DMAMUX1 clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): DMAMUX1 clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
CORDICSMEN	CORDICSM clock enable. Set and cleared by software. 0 (B_0x0): CORDICSM clocks disabled. 1 (B_0x1): CORDICSM clocks enabled.
FMACSMEN	FMACSM clock enable. Set and cleared by software. 0 (B_0x0): FMACSM clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): FMACSM clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
FLASHSMEN	Flash memory interface clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): Flash memory interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): Flash memory interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
SRAM1SMEN	SRAM1 interface clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): SRAM1 interface clocks disabled by the clock gating⁽¹⁾ during Sleep and Stop modes 1 (B_0x1): SRAM1 interface clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes
CRCSMEN	CRC clocks enable during Sleep and Stop modes Set and cleared by software. 0 (B_0x0): CRC clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): CRC clocks enabled by the clock gating⁽¹⁾ during Sleep and Stop modes

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