LSCOEN=B_0x0, RTCSEL=B_0x0, LSERDY=B_0x0, BDRST=B_0x0, LSECSSD=B_0x0, LSCOSEL=B_0x0, RTCEN=B_0x0, LSEDRV=B_0x0, LSECSSON=B_0x0, LSEON=B_0x0, LSEBYP=B_0x0
RTC domain control register
| LSEON | LSE oscillator enable Set and cleared by software. 0 (B_0x0): LSE oscillator OFF 1 (B_0x1): LSE oscillator ON |
| LSERDY | LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 0 (B_0x0): LSE oscillator not ready 1 (B_0x1): LSE oscillator ready |
| LSEBYP | LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). 0 (B_0x0): LSE oscillator not bypassed 1 (B_0x1): LSE oscillator bypassed |
| LSEDRV | LSE oscillator drive capability Set by software to modulate the LSE oscillator’s drive capability. The oscillator is in Xtal mode when it is not in bypass mode. 0 (B_0x0): ‘Xtal mode’ lower driving capability 1 (B_0x1): ‘Xtal mode’ medium low driving capability 2 (B_0x2): ‘Xtal mode’ medium high driving capability 3 (B_0x3): ‘Xtal mode’ higher driving capability |
| LSECSSON | CSS on LSE enable Set by software to enable the Clock Security System on LSE (32 kHz oscillator). LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software MUST disable the LSECSSON bit. 0 (B_0x0): CSS on LSE (32 kHz external oscillator) OFF 1 (B_0x1): CSS on LSE (32 kHz external oscillator) ON |
| LSECSSD | CSS on LSE failure Detection Set by hardware to indicate when a failure has been detected by the Clock Security System on the external 32 kHz oscillator (LSE). 0 (B_0x0): No failure detected on LSE (32 kHz oscillator) 1 (B_0x1): Failure detected on LSE (32 kHz oscillator) |
| RTCSEL | RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them. 0 (B_0x0): No clock 1 (B_0x1): LSE oscillator clock used as RTC clock 2 (B_0x2): LSI oscillator clock used as RTC clock 3 (B_0x3): HSE oscillator clock divided by 32 used as RTC clock |
| RTCEN | RTC clock enable Set and cleared by software. 0 (B_0x0): RTC clock disabled 1 (B_0x1): RTC clock enabled |
| BDRST | RTC domain software reset Set and cleared by software. 0 (B_0x0): Reset not activated 1 (B_0x1): Reset the entire RTC domain |
| LSCOEN | Low speed clock output enable Set and cleared by software. 0 (B_0x0): Low speed clock output (LSCO) disable 1 (B_0x1): Low speed clock output (LSCO) enable |
| LSCOSEL | Low speed clock output selection Set and cleared by software. 0 (B_0x0): LSI clock selected 1 (B_0x1): LSE clock selected |