CSSF=B_0x0, LSERDYF=B_0x0, LSECSSF=B_0x0, LSIRDYF=B_0x0, PLLRDYF=B_0x0, HSERDYF=B_0x0, HSIRDYF=B_0x0, HSI48RDYF=B_0x0
Clock interrupt flag register
| LSIRDYF | LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0 (B_0x0): No clock ready interrupt caused by the LSI oscillator 1 (B_0x1): Clock ready interrupt caused by the LSI oscillator |
| LSERDYF | LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 0 (B_0x0): No clock ready interrupt caused by the LSE oscillator 1 (B_0x1): Clock ready interrupt caused by the LSE oscillator |
| HSIRDYF | HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. 0 (B_0x0): No clock ready interrupt caused by the HSI16 oscillator 1 (B_0x1): Clock ready interrupt caused by the HSI16 oscillator |
| HSERDYF | HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0 (B_0x0): No clock ready interrupt caused by the HSE oscillator 1 (B_0x1): Clock ready interrupt caused by the HSE oscillator |
| PLLRDYF | PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0 (B_0x0): No clock ready interrupt caused by PLL lock 1 (B_0x1): Clock ready interrupt caused by PLL lock |
| CSSF | Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. 0 (B_0x0): No clock security interrupt caused by HSE clock failure 1 (B_0x1): Clock security interrupt caused by HSE clock failure |
| LSECSSF | LSE Clock security system interrupt flag Set by hardware when a failure is detected in the LSE oscillator. Cleared by software setting the LSECSSC bit. 0 (B_0x0): No clock security interrupt caused by LSE clock failure 1 (B_0x1): Clock security interrupt caused by LSE clock failure |
| HSI48RDYF | HSI48 ready interrupt flag Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to Clock recovery RC register (RCC_CRRCR)). Cleared by software setting the HSI48RDYC bit. 0 (B_0x0): No clock ready interrupt caused by the HSI48 oscillator 1 (B_0x1): Clock ready interrupt caused by the HSI48 oscillator |