QUADSPI communication configuration register
| INSTRUCTION | Instruction Instruction to be send to the external SPI device. This field can be written only when BUSY = 0. |
| IMODE | Instruction mode This field defines the instruction phase mode of operation: This field can be written only when BUSY = 0. |
| ADMODE | Address mode This field defines the address phase mode of operation: This field can be written only when BUSY = 0. |
| ADSIZE | Address size This bit defines address size: This field can be written only when BUSY = 0. |
| ABMODE | Alternate bytes mode This field defines the alternate-bytes phase mode of operation: This field can be written only when BUSY = 0. |
| ABSIZE | Alternate bytes size This bit defines alternate bytes size: This field can be written only when BUSY = 0. |
| DCYC | Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31). This field can be written only when BUSY = 0. |
| DMODE | Data mode This field defines the data phases mode of operation: This field also determines the dummy phase mode of operation. This field can be written only when BUSY = 0. |
| FMODE | Functional mode This field defines the QUADSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE value. This field can be written only when BUSY = 0. |
| SIOO | Send instruction only once mode See Section15.3.11: Sending the instruction only once on page13. This bit has no effect when IMODE = 00. This field can be written only when BUSY = 0. |
| DHHC | DDR hold Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode: This feature is only active in DDR mode. This field can be written only when BUSY = 0. |
| DDRM | Double data rate mode This bit sets the DDR mode for the address, alternate byte and data phase: This field can be written only when BUSY = 0. |