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STMicroelectronics /STM32H7A3x /MDMA /C0IFCR

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Interpret as C0IFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CTEIF0)CTEIF0 0 (CCTCIF0)CCTCIF0 0 (CBRTIF0)CBRTIF0 0 (CBTIF0)CBTIF0 0 (CLTCIF0)CLTCIF0

Description

MDMA channel x interrupt flag clear register

Fields

CTEIF0

Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register
CCTCIF0

Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register
CBRTIF0

Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register
CBTIF0

Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register
CLTCIF0

CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data