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STMicroelectronics /STM32H7A3x /MDMA /C4ISR

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Interpret as C4ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TEIF4)TEIF4 0 (CTCIF4)CTCIF4 0 (BRTIF4)BRTIF4 0 (BTIF4)BTIF4 0 (TCIF4)TCIF4 0 (CRQA4)CRQA4

Description

MDMA channel x interrupt/status register

Fields

TEIF4

Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
CTCIF4

Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
BRTIF4

Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
BTIF4

Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
TCIF4

channel x buffer transfer complete
CRQA4

channel x request active flag

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data