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STMicroelectronics /STM32H7A3x /MDMA /C7ISR

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Interpret as C7ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TEIF7)TEIF7 0 (CTCIF7)CTCIF7 0 (BRTIF7)BRTIF7 0 (BTIF7)BTIF7 0 (TCIF7)TCIF7 0 (CRQA7)CRQA7

Description

MDMA channel x interrupt/status register

Fields

TEIF7

Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
CTCIF7

Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
BRTIF7

Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
BTIF7

Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
TCIF7

channel x buffer transfer complete
CRQA7

channel x request active flag

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data