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STMicroelectronics /STM32H7x7_CM4 /HSEM /HSEM_MISR

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Interpret as HSEM_MISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MISF0)MISF0 0 (MISF1)MISF1 0 (MISF2)MISF2 0 (MISF3)MISF3 0 (MISF4)MISF4 0 (MISF5)MISF5 0 (MISF6)MISF6 0 (MISF7)MISF7 0 (MISF8)MISF8 0 (MISF9)MISF9 0 (MISF10)MISF10 0 (MISF11)MISF11 0 (MISF12)MISF12 0 (MISF13)MISF13 0 (MISF14)MISF14 0 (MISF15)MISF15 0 (MISF16)MISF16 0 (MISF17)MISF17 0 (MISF18)MISF18 0 (MISF19)MISF19 0 (MISF20)MISF20 0 (MISF21)MISF21 0 (MISF22)MISF22 0 (MISF23)MISF23 0 (MISF24)MISF24 0 (MISF25)MISF25 0 (MISF26)MISF26 0 (MISF27)MISF27 0 (MISF28)MISF28 0 (MISF29)MISF29 0 (MISF30)MISF30 0 (MISF31)MISF31

Description

HSEM Masked interrupt status register

Fields

MISF0

Interrupt(N) semaphore n status bit before enable (mask)
MISF1

Interrupt(N) semaphore n status bit before enable (mask)
MISF2

Interrupt(N) semaphore n status bit before enable (mask)
MISF3

masked interrupt(N) semaphore n status bit after enable (mask).
MISF4

masked interrupt(N) semaphore n status bit after enable (mask).
MISF5

masked interrupt(N) semaphore n status bit after enable (mask).
MISF6

masked interrupt(N) semaphore n status bit after enable (mask).
MISF7

masked interrupt(N) semaphore n status bit after enable (mask).
MISF8

masked interrupt(N) semaphore n status bit after enable (mask).
MISF9

masked interrupt(N) semaphore n status bit after enable (mask).
MISF10

masked interrupt(N) semaphore n status bit after enable (mask).
MISF11

masked interrupt(N) semaphore n status bit after enable (mask).
MISF12

masked interrupt(N) semaphore n status bit after enable (mask).
MISF13

masked interrupt(N) semaphore n status bit after enable (mask).
MISF14

masked interrupt(N) semaphore n status bit after enable (mask).
MISF15

masked interrupt(N) semaphore n status bit after enable (mask).
MISF16

masked interrupt(N) semaphore n status bit after enable (mask).
MISF17

masked interrupt(N) semaphore n status bit after enable (mask).
MISF18

masked interrupt(N) semaphore n status bit after enable (mask).
MISF19

masked interrupt(N) semaphore n status bit after enable (mask).
MISF20

masked interrupt(N) semaphore n status bit after enable (mask).
MISF21

masked interrupt(N) semaphore n status bit after enable (mask).
MISF22

masked interrupt(N) semaphore n status bit after enable (mask).
MISF23

masked interrupt(N) semaphore n status bit after enable (mask).
MISF24

masked interrupt(N) semaphore n status bit after enable (mask).
MISF25

masked interrupt(N) semaphore n status bit after enable (mask).
MISF26

masked interrupt(N) semaphore n status bit after enable (mask).
MISF27

masked interrupt(N) semaphore n status bit after enable (mask).
MISF28

masked interrupt(N) semaphore n status bit after enable (mask).
MISF29

masked interrupt(N) semaphore n status bit after enable (mask).
MISF30

masked interrupt(N) semaphore n status bit after enable (mask).
MISF31

masked interrupt(N) semaphore n status bit after enable (mask).

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data