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STMicroelectronics /STM32L0x1 /RCC /APB1RSTR

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Interpret as APB1RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2RST)TIM2RST 0 (TIM3RST)TIM3RST 0 (TIM6RST)TIM6RST 0 (TIM7RST)TIM7RST 0 (WWDGRST)WWDGRST 0 (SPI2RST)SPI2RST 0 (USART2RST)USART2RST 0 (LPUART1RST)LPUART1RST 0 (USART4RST)USART4RST 0 (USART5RST)USART5RST 0 (I2C1RST)I2C1RST 0 (I2C2RST)I2C2RST 0 (CRCRST)CRCRST 0 (PWRRST)PWRRST 0 (I2C3)I2C3 0 (LPTIM1RST)LPTIM1RST

Description

APB1 peripheral reset register

Fields

TIM2RST

Timer 2 reset
TIM3RST

Timer 3 reset
TIM6RST

Timer 6 reset
TIM7RST

Timer 7 reset
WWDGRST

Window watchdog reset
SPI2RST

SPI2 reset
USART2RST

USART2 reset
LPUART1RST

LPUART1 reset
USART4RST

USART4 reset
USART5RST

USART5 reset
I2C1RST

I2C1 reset
I2C2RST

I2C2 reset
CRCRST

CRC reset
PWRRST

Power interface reset
I2C3

I2C3 reset
LPTIM1RST

Low power timer reset

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data