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STMicroelectronics /STM32L0x1 /RCC /CICR

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Interpret as CICR

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https://regviz.com/r/STMicroelectronics/STM32L0x1/RCC/CICR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSIRDYC)LSIRDYC 0 (LSERDYC)LSERDYC 0 (HSI16RDYC)HSI16RDYC 0 (HSERDYC)HSERDYC 0 (PLLRDYC)PLLRDYC 0 (MSIRDYC)MSIRDYC 0 (CSSLSEC)CSSLSEC 0 (CSSHSEC)CSSHSEC

Description

Clock interrupt clear register

Fields

LSIRDYC

LSI ready Interrupt clear
LSERDYC

LSE ready Interrupt clear
HSI16RDYC

HSI16 ready Interrupt clear
HSERDYC

HSE ready Interrupt clear
PLLRDYC

PLL ready Interrupt clear
MSIRDYC

MSI ready Interrupt clear
CSSLSEC

LSE Clock Security System Interrupt clear
CSSHSEC

Clock Security System Interrupt clear

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data