Control and status register
| LSION | Internal low-speed oscillator enable |
| LSIRDY | Internal low-speed oscillator ready bit |
| LSIIWDGLP | LSI clock input to IWDG in Ultra-low-power mode (Stop and Standby) enable bit |
| LSEON | External low-speed oscillator enable bit |
| LSERDY | External low-speed oscillator ready bit |
| LSEBYP | External low-speed oscillator bypass bit |
| LSEDRV | LSEDRV |
| CSSLSEON | CSSLSEON |
| CSSLSED | CSS on LSE failure detection flag |
| RTCSEL | RTC and LCD clock source selection bits |
| RTCEN | RTC clock enable bit |
| RTCRST | RTC software reset bit |
| RMVF | Remove reset flag |
| FWRSTF | Firewall reset flag |
| OBLRSTF | OBLRSTF |
| PINRSTF | PIN reset flag |
| PORRSTF | POR/PDR reset flag |
| SFTRSTF | Software reset flag |
| IWDGRSTF | Independent watchdog reset flag |
| WWDGRSTF | Window watchdog reset flag |
| LPWRSTF | Low-power reset flag |