STMicroelectronics /STM32L0x2 /RCC /CSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSION)LSION 0 (LSIRDY)LSIRDY 0 (LSEON)LSEON 0 (LSERDY)LSERDY 0 (LSEBYP)LSEBYP 0LSEDRV 0 (CSSLSEON)CSSLSEON 0 (CSSLSED)CSSLSED 0RTCSEL 0 (RTCEN)RTCEN 0 (RTCRST)RTCRST 0 (RMVF)RMVF 0 (OBLRSTF)OBLRSTF 0 (PINRSTF)PINRSTF 0 (PORRSTF)PORRSTF 0 (SFTRSTF)SFTRSTF 0 (IWDGRSTF)IWDGRSTF 0 (WWDGRSTF)WWDGRSTF 0 (LPWRSTF)LPWRSTF

Description

Control and status register

Fields

LSION

Internal low-speed oscillator enable

LSIRDY

Internal low-speed oscillator ready bit

LSEON

External low-speed oscillator enable bit

LSERDY

External low-speed oscillator ready bit

LSEBYP

External low-speed oscillator bypass bit

LSEDRV

LSEDRV

CSSLSEON

CSSLSEON

CSSLSED

CSS on LSE failure detection flag

RTCSEL

RTC and LCD clock source selection bits

RTCEN

RTC clock enable bit

RTCRST

RTC software reset bit

RMVF

Remove reset flag

OBLRSTF

OBLRSTF

PINRSTF

PIN reset flag

PORRSTF

POR/PDR reset flag

SFTRSTF

Software reset flag

IWDGRSTF

Independent watchdog reset flag

WWDGRSTF

Window watchdog reset flag

LPWRSTF

Low-power reset flag

Links

()