STMicroelectronics /STM32L100 /RCC /AHBLPENR

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Interpret as AHBLPENR

31282724232019161512118743000000000000000000000000000000000000000000 (GPIOALPEN)GPIOALPEN0 (GPIOBLPEN)GPIOBLPEN0 (GPIOCLPEN)GPIOCLPEN0 (GPIODLPEN)GPIODLPEN0 (CRCLPEN)CRCLPEN0 (FLITFLPEN)FLITFLPEN0 (SRAMLPEN)SRAMLPEN0 (DMALPEN)DMALPEN

Description

AHB peripheral clock enable in low power mode register

Fields

GPIOALPEN

IO port A clock enable during Sleep mode

GPIOBLPEN

IO port B clock enable during Sleep mode

GPIOCLPEN

IO port C clock enable during Sleep mode

GPIODLPEN

IO port D clock enable during Sleep mode

CRCLPEN

CRC clock enable during Sleep mode

FLITFLPEN

FLITF clock enable during Sleep mode

SRAMLPEN

SRAM clock enable during Sleep mode

DMALPEN

DMA1 clock enable during Sleep mode

Links

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