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STMicroelectronics /STM32L4x1 /RCC /CIER

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Interpret as CIER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSIRDYIE)LSIRDYIE 0 (LSERDYIE)LSERDYIE 0 (MSIRDYIE)MSIRDYIE 0 (HSIRDYIE)HSIRDYIE 0 (HSERDYIE)HSERDYIE 0 (PLLRDYIE)PLLRDYIE 0 (PLLSAI1RDYIE)PLLSAI1RDYIE 0 (LSECSSIE)LSECSSIE 0 (HSI48RDYIE)HSI48RDYIE

Description

Clock interrupt enable register

Fields

LSIRDYIE

LSI ready interrupt enable
LSERDYIE

LSE ready interrupt enable
MSIRDYIE

MSI ready interrupt enable
HSIRDYIE

HSI ready interrupt enable
HSERDYIE

HSE ready interrupt enable
PLLRDYIE

PLL ready interrupt enable
PLLSAI1RDYIE

PLLSAI1 ready interrupt enable
LSECSSIE

LSE clock security system interrupt enable
HSI48RDYIE

HSI48 ready interrupt enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data