Regviz

STMicroelectronics /STM32L4x3 /SYSCFG /CFGR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CFGR2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32L4x3/SYSCFG/CFGR2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLL)CLL 0 (SPL)SPL 0 (PVDL)PVDL 0 (ECCL)ECCL 0 (SPF)SPF

Description

CFGR2

Fields

CLL

Cortexâ„¢-M4 LOCKUP (Hardfault) output enable bit
SPL

SRAM2 parity lock bit
PVDL

PVD lock enable bit
ECCL

ECC Lock
SPF

SRAM2 parity error flag

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data