Regviz

STMicroelectronics /STM32L552 /TIM15 /SMCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SMCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32L562/TIM15/SMCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMS0TS0 (MSM)MSM 0 (SMS_bit3)SMS_bit3

Description

TIM15 slave mode control register

Fields

SMS

Slave mode selection
TS

Trigger selection
MSM

Master/slave mode
SMS_bit3

Slave mode selection - bit 3

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data