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STMicroelectronics /STM32L562 /TIM15 /SMCR

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Interpret as SMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMS0TS0 (MSM)MSM 0 (SMS_bit3)SMS_bit3

Description

TIM15 slave mode control register

Fields

SMS

Slave mode selection
TS

Trigger selection
MSM

Master/slave mode
SMS_bit3

Slave mode selection - bit 3

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data