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STMicroelectronics /STM32L562 /RCC /APB1SMENR2

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Interpret as APB1SMENR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPUART1SMEN)LPUART1SMEN 0 (I2C4SMEN)I2C4SMEN 0 (LPTIM2SMEN)LPTIM2SMEN 0 (LPTIM3SMEN)LPTIM3SMEN 0 (FDCAN1SMEN)FDCAN1SMEN 0 (USBFSSMEN)USBFSSMEN 0 (UCPD1SMEN)UCPD1SMEN

Description

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Fields

LPUART1SMEN

Low power UART 1 clocks enable during Sleep and Stop modes
I2C4SMEN

I2C4 clocks enable during Sleep and Stop modes
LPTIM2SMEN

LPTIM2SMEN
LPTIM3SMEN

LPTIM3SMEN
FDCAN1SMEN

FDCAN1SMEN
USBFSSMEN

USBFSSMEN
UCPD1SMEN

UCPD1SMEN

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data