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STMicroelectronics /STM32L562 /RCC /BDCR

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Interpret as BDCR

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https://regviz.com/r/STMicroelectronics/STM32L562/RCC/BDCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSEON)LSEON 0 (LSERDY)LSERDY 0 (LSEBYP)LSEBYP 0LSEDRV 0 (LSECSSON)LSECSSON 0 (LSECSSD)LSECSSD 0 (LSESYSEN)LSESYSEN 0RTCSEL 0 (LSESYSRDY)LSESYSRDY 0 (RTCEN)RTCEN 0 (BDRST)BDRST 0 (LSCOEN)LSCOEN 0 (LSCOSEL)LSCOSEL

Description

BDCR

Fields

LSEON

LSE oscillator enable
LSERDY

LSE oscillator ready
LSEBYP

LSE oscillator bypass
LSEDRV

SE oscillator drive capability
LSECSSON

LSECSSON
LSECSSD

LSECSSD
LSESYSEN

LSESYSEN
RTCSEL

RTC clock source selection
LSESYSRDY

LSESYSRDY
RTCEN

RTC clock enable
BDRST

Backup domain software reset
LSCOEN

Low speed clock output enable
LSCOSEL

Low speed clock output selection

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data