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STMicroelectronics /STM32L562 /RCC /PLLSAI2CFGR

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Interpret as PLLSAI2CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLLSAI2SRC 0PLLSAI2M 0PLLSAI2N0 (PLLSAI2PEN)PLLSAI2PEN 0 (PLLSAI2P)PLLSAI2P 0PLLSAI2PDIV

Description

PLLSAI2 configuration register

Fields

PLLSAI2SRC

PLLSAI2SRC
PLLSAI2M

Division factor for PLLSAI2 input clock
PLLSAI2N

SAI2PLL multiplication factor for VCO
PLLSAI2PEN

SAI2PLL PLLSAI2CLK output enable
PLLSAI2P

SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)
PLLSAI2PDIV

PLLSAI2 division factor for PLLSAI2CLK

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data