The SDMMC_DCTRL register control the data path state machine (DPSM).
| DTEN | Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards. |
| DTDIR | Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). |
| DTMODE | Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). |
| DBLOCKSIZE | Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered) |
| RWSTART | Read wait start. If this bit is set, read wait operation starts. |
| RWSTOP | Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state. |
| RWMOD | Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). |
| SDIOEN | SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. |
| BOOTACKEN | Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). |
| FIFORST | FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs. |