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STMicroelectronics /STM32L562 /SDMMC1 /SDMMC_IDMACTRLR

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Interpret as SDMMC_IDMACTRLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IDMAEN)IDMAEN 0 (IDMABMODE)IDMABMODE 0 (IDMABACT)IDMABACT

Description

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Fields

IDMAEN

IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
IDMABMODE

Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
IDMABACT

Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data