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STMicroelectronics /STM32L562 /TIM15 /OR1

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Interpret as OR1

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https://regviz.com/r/STMicroelectronics/STM32L562/TIM15/OR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TI1_RMP)TI1_RMP 0ENCODER_MODE

Description

TIM15 option register 1

Fields

TI1_RMP

Input capture 1 remap
ENCODER_MODE

Encoder mode

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data