DMAEN1=B_0x0, TSEL1=B_0x0, CEN1=B_0x0, MAMP1=B_0x0, EN1=B_0x0, DMAUDRIE1=B_0x0, WAVE1=B_0x0, TEN1=B_0x0
DAC control register
| EN1 | DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0 (B_0x0): DAC channel1 disabled 1 (B_0x1): DAC channel1 enabled |
| TEN1 | DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle. 0 (B_0x0): DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register 1 (B_0x1): DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register |
| TSEL1 | DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 … Refer to the trigger selection tables in Section114.4.2: DAC pins and internal signals for details on trigger configuration and mapping. Note: Only used if bit TEN11=11 (DAC channel1 trigger enabled). 0 (B_0x0): SWTRIG1 1 (B_0x1): dac_ch1_trg1 2 (B_0x2): dac_ch1_trg2 15 (B_0xF): dac_ch1_trg15 |
| WAVE1 | DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 1x: Triangle wave generation enabled Only used if bit TEN11=11 (DAC channel1 trigger enabled). 0 (B_0x0): wave generation disabled 1 (B_0x1): Noise wave generation enabled |
| MAMP1 | DAC channel1 mask/amplitude selector 0 (B_0x0): Unmask bit0 of LFSR/ triangle amplitude equal to 1 1 (B_0x1): Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 2 (B_0x2): Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 3 (B_0x3): Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 4 (B_0x4): Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 5 (B_0x5): Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 6 (B_0x6): Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 7 (B_0x7): Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 8 (B_0x8): Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 9 (B_0x9): Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 10 (B_0xA): Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 |
| DMAEN1 | DAC channel1 DMA enable This bit is set and cleared by software. 0 (B_0x0): DAC channel1 DMA mode disabled 1 (B_0x1): DAC channel1 DMA mode enabled |
| DMAUDRIE1 | DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 0 (B_0x0): DAC channel1 DMA Underrun Interrupt disabled 1 (B_0x1): DAC channel1 DMA Underrun Interrupt enabled |
| CEN1 | DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN11=10 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. 0 (B_0x0): DAC channel1 in Normal operating mode 1 (B_0x1): DAC channel1 in calibration mode |