EM31=B_0x0, EM3=B_0x0, EM6=B_0x0, EM30=B_0x0, EM19=B_0x0, EM17=B_0x0, EM10=B_0x0, EM12=B_0x0, EM9=B_0x0, EM2=B_0x0, EM0=B_0x0, EM27=B_0x0, EM22=B_0x0, EM20=B_0x0, EM18=B_0x0, EM24=B_0x0, EM15=B_0x0, EM4=B_0x0, EM25=B_0x0, EM11=B_0x0, EM16=B_0x0, EM14=B_0x0, EM29=B_0x0, EM21=B_0x0, EM8=B_0x0, EM28=B_0x0, EM23=B_0x0, EM5=B_0x0, EM1=B_0x0, EM26=B_0x0, EM7=B_0x0, EM13=B_0x0
EXTI CPU wake-up with event mask register
| EM0 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM1 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM2 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM3 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM4 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM5 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM6 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM7 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM8 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM9 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM10 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM11 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM12 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM13 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM14 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM15 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM16 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM17 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM18 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM19 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM20 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM21 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM22 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM23 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM24 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM25 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM26 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM27 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM28 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM29 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM30 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |
| EM31 | CPU wake-up with event generation mask on line x (x1=1311to10) Setting/clearing each bit unmasks/masks the CPU wake-up with event generation on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices. 0 (B_0x0): wake-up with event generation masked 1 (B_0x1): wake-up with event generation unmasked |