STMicroelectronics /STM32U031 /I2C1 /I2C_CR1

Peripheral enable Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least three APB clock cycles.

0 (B_0x0): Peripheral disable

1 (B_0x1): Peripheral enable

TX interrupt enable

0 (B_0x0): Transmit (TXIS) interrupt disabled

1 (B_0x1): Transmit (TXIS) interrupt enabled

RX interrupt enable

0 (B_0x0): Receive (RXNE) interrupt disabled

1 (B_0x1): Receive (RXNE) interrupt enabled

Address match interrupt enable (slave only)

0 (B_0x0): Address match (ADDR) interrupts disabled

1 (B_0x1): Address match (ADDR) interrupts enabled

Not acknowledge received interrupt enable

0 (B_0x0): Not acknowledge (NACKF) received interrupts disabled

1 (B_0x1): Not acknowledge (NACKF) received interrupts enabled

Stop detection interrupt enable

0 (B_0x0): Stop detection (STOPF) interrupt disabled

1 (B_0x1): Stop detection (STOPF) interrupt enabled

Transfer complete interrupt enable Note: Any of these events generate an interrupt: Note: Transfer complete (TC) Note: Transfer complete reload (TCR)

0 (B_0x0): Transfer complete interrupt disabled

1 (B_0x1): Transfer complete interrupt enabled

Error interrupts enable Note: Any of these errors generate an interrupt: Note: Arbitration loss (ARLO) Note: Bus error detection (BERR) Note: Overrun/Underrun (OVR)

0 (B_0x0): Error detection interrupts disabled

1 (B_0x1): Error detection interrupts enabled

Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t_{I2CCLK …} Note: If the analog filter is enabled, the digital filter is added to it. This filter can be programmed only when the I2C is disabled (PE = 0).

0 (B_0x0): Digital filter disabled

1 (B_0x1): Digital filter enabled and filtering capability up to 1 t_I2CCLK

15 (B_0xF): digital filter enabled and filtering capability up to15 t_I2CCLK

Analog noise filter OFF Note: This bit can be programmed only when the I2C is disabled (PE = 0).

0 (B_0x0): Analog noise filter enabled

1 (B_0x1): Analog noise filter disabled

DMA transmission requests enable

0 (B_0x0): DMA mode disabled for transmission

1 (B_0x1): DMA mode enabled for transmission

DMA reception requests enable

0 (B_0x0): DMA mode disabled for reception

1 (B_0x1): DMA mode enabled for reception

Slave byte control This bit is used to enable hardware byte control in slave mode.

0 (B_0x0): Slave byte control disabled

1 (B_0x1): Slave byte control enabled

Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can be programmed only when the I2C is disabled (PE = 0).

0 (B_0x0): Clock stretching enabled

1 (B_0x1): Clock stretching disabled

Wake-up from Stop mode enable

0 (B_0x0): Wake-up from Stop mode disable.

1 (B_0x1): Wake-up from Stop mode enable.

General call enable

0 (B_0x0): General call disabled. Address 0b00000000 is NACKed.

1 (B_0x1): General call enabled. Address 0b00000000 is ACKed.

Fast-mode Plus 20 mA drive enable

0 (B_0x0): 20 mA I/O drive disabled

1 (B_0x1): 20 mA I/O drive enabled

Address match flag (ADDR) automatic clear

0 (B_0x0): ADDR flag is set by hardware, cleared by software by setting ADDRCF bit.

1 (B_0x1): ADDR flag remains cleared by hardware. This mode can be used in slave mode, to avoid the ADDR clock stretching if the I2C enables only one slave address. This allows a slave data management by DMA only, without any interrupt from peripheral.

STOP detection flag (STOPF) automatic clear

0 (B_0x0): STOPF flag is set by hardware, cleared by software by setting STOPCF bit.

1 (B_0x1): STOPF flag remains cleared by hardware. This mode can be used in NOSTRETCH slave mode, to avoid the overrun error if the STOPF flag is not cleared before next data transmission. This allows a slave data management by DMA only, without any interrupt from peripheral.