UEIE=B_0x0, CMP4OKIE=B_0x0, DOWNIE=B_0x0, UPIE=B_0x0, CC1IE=B_0x0, CMP2OKIE=B_0x0, CC2IE=B_0x0, CC4IE=B_0x0, EXTTRIGIE=B_0x0, UEDE=B_0x0, REPOKIE=B_0x0, ARROKIE=B_0x0, CC3IE=B_0x0, CMP1OKIE=B_0x0, CMP3OKIE=B_0x0, ARRMIE=B_0x0
LPTIM1 interrupt enable register [alternate]
| CC1IE | Capture/compare 1 interrupt enable 0 (B_0x0): Capture/compare 1 interrupt disabled 1 (B_0x1): Capture/compare 1 interrupt enabled |
| ARRMIE | Autoreload match Interrupt Enable 0 (B_0x0): ARRM interrupt disabled 1 (B_0x1): ARRM interrupt enabled |
| EXTTRIGIE | External trigger valid edge Interrupt Enable 0 (B_0x0): EXTTRIG interrupt disabled 1 (B_0x1): EXTTRIG interrupt enabled |
| CMP1OKIE | Compare register 1 update OK interrupt enable 0 (B_0x0): CMPOK register 1 interrupt disabled 1 (B_0x1): CMPOK register 1 interrupt enabled |
| ARROKIE | Autoreload register update OK Interrupt Enable 0 (B_0x0): ARROK interrupt disabled 1 (B_0x1): ARROK interrupt enabled |
| UPIE | Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. 0 (B_0x0): UP interrupt disabled 1 (B_0x1): UP interrupt enabled |
| DOWNIE | Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. 0 (B_0x0): DOWN interrupt disabled 1 (B_0x1): DOWN interrupt enabled |
| UEIE | Update event interrupt enable 0 (B_0x0): Update event interrupt disabled 1 (B_0x1): Update event interrupt enabled |
| REPOKIE | Repetition register update OK interrupt Enable 0 (B_0x0): Repetition register update OK interrupt disabled 1 (B_0x1): Repetition register update OK interrupt enabled |
| CC2IE | Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): Capture/compare 2 interrupt disabled 1 (B_0x1): Capture/compare 2 interrupt enabled |
| CC3IE | Capture/compare 3 interrupt enable Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): Capture/compare 3 interrupt disabled 1 (B_0x1): Capture/compare 3 interrupt enabled |
| CC4IE | Capture/compare 4 interrupt enable Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): Capture/compare 4 interrupt disabled 1 (B_0x1): Capture/compare 4 interrupt enabled |
| CMP2OKIE | Compare register 2 update OK interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): CMPOK register 2 interrupt disabled 1 (B_0x1): CMPOK register 2 interrupt enabled |
| CMP3OKIE | Compare register 3 update OK interrupt enable Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): CMPOK register 3 interrupt disabled 1 (B_0x1): CMPOK register 3 interrupt enabled |
| CMP4OKIE | Compare register 4 update OK interrupt enable Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): CMPOK register 4 interrupt disabled 1 (B_0x1): CMPOK register 4 interrupt enabled |
| UEDE | Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. 0 (B_0x0): UE DMA request disabled. Writing ‘0’ to the UEDE bit resets the associated ue_dma_req signal. 1 (B_0x1): UE DMA request enabled |