TRGFLT=B_0x0, CKFLT=B_0x0, TRIGSEL=B_0x0, CKPOL=B_0x0, TRIGEN=B_0x0, PRESC=B_0x0, CKSEL=B_0x0, COUNTMODE=B_0x0, PRELOAD=B_0x0, ENC=B_0x0, WAVE=B_0x0, TIMOUT=B_0x0
LPTIM configuration register
| CKSEL | Clock selector The CKSEL bit selects which clock source the LPTIM uses: 0 (B_0x0): LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 1 (B_0x1): LPTIM is clocked by an external clock source through the LPTIM external Input1 |
| CKPOL | Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. Refer to Section125.4.15: Encoder mode for more details about Encoder mode sub-modes. 0 (B_0x0): the rising edge is the active edge used for counting. 1 (B_0x1): the falling edge is the active edge used for counting. 2 (B_0x2): both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. 3 (B_0x3): not allowed |
| CKFLT | Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 0 (B_0x0): any external clock signal level change is considered as a valid transition 1 (B_0x1): external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 2 (B_0x2): external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 3 (B_0x3): external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. |
| TRGFLT | Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that are detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 0 (B_0x0): any trigger active level change is considered as a valid trigger 1 (B_0x1): trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 2 (B_0x2): trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 3 (B_0x3): trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. |
| PRESC | Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 0 (B_0x0): /1 1 (B_0x1): /2 2 (B_0x2): /4 3 (B_0x3): /8 4 (B_0x4): /16 5 (B_0x5): /32 6 (B_0x6): /64 7 (B_0x7): /128 |
| TRIGSEL | Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See Section125.4.3: LPTIM input and trigger mapping for details. 0 (B_0x0): LPTIM2_ext_trig0 1 (B_0x1): LPTIM2_ext_trig1 2 (B_0x2): LPTIM2_ext_trig2 3 (B_0x3): LPTIM2_ext_trig3 4 (B_0x4): LPTIM2_ext_trig4 5 (B_0x5): LPTIM2_ext_trig5 6 (B_0x6): LPTIM2_ext_trig6 7 (B_0x7): LPTIM2_ext_trig7 |
| TRIGEN | Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 0 (B_0x0): software trigger (counting start is initiated by software) 1 (B_0x1): rising edge is the active edge 2 (B_0x2): falling edge is the active edge 3 (B_0x3): both edges are active edges |
| TIMOUT | Timeout enable The TIMOUT bit controls the Timeout feature 0 (B_0x0): A trigger event arriving when the timer is already started is ignored 1 (B_0x1): A trigger event arriving when the timer is already started resets and restarts the LPTIM counter and the repetition counter |
| WAVE | Waveform shape The WAVE bit controls the output shape 0 (B_0x0): Deactivate Set-once mode 1 (B_0x1): Activate the Set-once mode |
| PRELOAD | Registers update mode The PRELOAD bit controls the LPTIM2_ARR, LPTIM2_RCR and the LPTIM2_CCRx registers update modality 0 (B_0x0): Registers are updated after each APB bus write access 1 (B_0x1): Registers are updated at the end of the current LPTIM period |
| COUNTMODE | counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: 0 (B_0x0): the counter is incremented following each internal clock pulse 1 (B_0x1): the counter is incremented following each valid clock pulse on the LPTIM external Input1 |
| ENC | Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. 0 (B_0x0): Encoder mode disabled 1 (B_0x1): Encoder mode enabled |