ARRMIE=B_0x0, CC1IE=B_0x0, CC2DE=B_0x0, UEIE=B_0x0, CC3IE=B_0x0, DOWNIE=B_0x0, CC2IE=B_0x0, CC3OIE=B_0x0, UPIE=B_0x0, CC1OIE=B_0x0, REPOKIE=B_0x0, EXTTRIGIE=B_0x0, CC4DE=B_0x0, CC3DE=B_0x0, CC4OIE=B_0x0, CC2OIE=B_0x0, UEDE=B_0x0, CC4IE=B_0x0, CC1DE=B_0x0, ARROKIE=B_0x0
LPTIM2 interrupt enable register [alternate]
| CC1IE | Capture/compare 1 interrupt enable 0 (B_0x0): Capture/compare 1 interrupt disabled 1 (B_0x1): Capture/compare 1 interrupt enabled |
| ARRMIE | Autoreload match Interrupt Enable 0 (B_0x0): ARRM interrupt disabled 1 (B_0x1): ARRM interrupt enabled |
| EXTTRIGIE | External trigger valid edge Interrupt Enable 0 (B_0x0): EXTTRIG interrupt disabled 1 (B_0x1): EXTTRIG interrupt enabled |
| ARROKIE | Autoreload register update OK Interrupt Enable 0 (B_0x0): ARROK interrupt disabled 1 (B_0x1): ARROK interrupt enabled |
| UPIE | Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. 0 (B_0x0): UP interrupt disabled 1 (B_0x1): UP interrupt enabled |
| DOWNIE | Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3. 0 (B_0x0): DOWN interrupt disabled 1 (B_0x1): DOWN interrupt enabled |
| UEIE | Update event interrupt enable 0 (B_0x0): Update event interrupt disabled 1 (B_0x1): Update event interrupt enabled |
| REPOKIE | Repetition register update OK interrupt Enable 0 (B_0x0): Repetition register update OK interrupt disabled 1 (B_0x1): Repetition register update OK interrupt enabled |
| CC2IE | Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): Capture/compare 2 interrupt disabled 1 (B_0x1): Capture/compare 2 interrupt enabled |
| CC3IE | Capture/compare 3 interrupt enable Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): Capture/compare 3 interrupt disabled 1 (B_0x1): Capture/compare 3 interrupt enabled |
| CC4IE | Capture/compare 4 interrupt enable Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): Capture/compare 4 interrupt disabled 1 (B_0x1): Capture/compare 4 interrupt enabled |
| CC1OIE | Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. 0 (B_0x0): CC1 over-capture interrupt disabled 1 (B_0x1): CC1 over-capture interrupt enabled |
| CC2OIE | Capture/compare 2 over-capture interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): CC2 over-capture interrupt disabled 1 (B_0x1): CC2 over-capture interrupt enabled |
| CC3OIE | Capture/compare 3 over-capture interrupt enable Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): CC3 over-capture interrupt disabled 1 (B_0x1): CC3 over-capture interrupt enabled |
| CC4OIE | Capture/compare 4 over-capture interrupt enable Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): CC4 over-capture interrupt disabled 1 (B_0x1): CC4 over-capture interrupt enabled |
| CC1DE | Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. 0 (B_0x0): CC1 DMA request disabled. Writing ‘0’ to the CC1DE bit resets the associated ic1_dma_req signal. 1 (B_0x1): CC1 DMA request enabled |
| UEDE | Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3. 0 (B_0x0): UE DMA request disabled. Writing ‘0’ to the UEDE bit resets the associated ue_dma_req signal. 1 (B_0x1): UE DMA request enabled |
| CC2DE | Capture/compare 2 DMA request enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): CC2 DMA request disabled. Writing ‘0’ to the CC2DE bit resets the associated ic2_dma_req signal. 1 (B_0x1): CC2 DMA request enabled |
| CC3DE | Capture/compare 3 DMA request enable Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): CC3 DMA request disabled. Writing ‘0’ to the CC3DE bit resets the associated ic3_dma_req signal. 1 (B_0x1): CC3 DMA request enabled |
| CC4DE | Capture/compare 4 DMA request enable Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3. 0 (B_0x0): CC4 DMA request disabled. Writing ‘0’ to the CC4DE bit resets the associated ic4_dma_req signal. 1 (B_0x1): CC4 DMA request enabled |