ADDM7=B_0x0, DATAINV=B_0x0, TXINV=B_0x0, MSBFIRST=B_0x0, STOP=B_0x0, SWAP=B_0x0, RXINV=B_0x0
LPUART control register 2
| ADDM7 | 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the LPUART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively. 0 (B_0x0): 4-bit address detection 1 (B_0x1): 7-bit address detection (in 8-bit data mode) |
| STOP | STOP bits These bits are used for programming the stop bits. This bitfield can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): 1 stop bit 1 (B_0x1): Reserved. 2 (B_0x2): 2 stop bits |
| SWAP | Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): TX/RX pins are used as defined in standard pinout 1 (B_0x1): The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART. |
| RXINV | RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1 (B_0x1): RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). |
| TXINV | TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) 1 (B_0x1): TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). |
| DATAINV | Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1 (B_0x1): Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. |
| MSBFIRST | Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): data is transmitted/received with data bit 0 first, following the start bit. 1 (B_0x1): data is transmitted/received with the MSB (bit 7/8) first, following the start bit. |
| ADD | Address of the LPUART node These bits give the address of the LPUART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE1=10) or when the USART is disabled (UE1=10). |